1. Field of Invention
The present invention relates to a method for manufacturing a charge storage electrode. More particularly, the present invention relates to a method for manufacturing the charge storage electrode of a capacitor in high density DRAM.
2. Description of Related Art
DRAMs use an array of capacitors fabricated on a semiconductor substrate to store digital data. In general, the charge storage states are utilized to store a bit of data. Normally, a capacitor with charges is regarded as in a logic "1" state, and a capacitor without stored charges is regarded as in a logic "0" state. Hence, a single bit of binary data is stored in a capacitor. The charge storage capacity of a capacitor depends on several factors including surface area within the electrode of a capacitor, the reliability of the electrode isolation and the dielectric constant of the dielectric layer between the electrodes of a capacitor. Storage and retrieval of data to and from memory as well as reading and writing operations are executed by the transfer of charges to or from the capacitor through a transfer field effect transistor (FET), which is coupled to a bit line. The bit line is connected to one source/drain terminal of the transfer FET, while the charge storage capacitor is connected to the other source/drain terminal of the transfer FET. A word line is connected to the gate of the transfer FET. Control signals can then be sent through the word line to the gate of the transfer FET, thereby switching open the transistor. Hence, an electrical connection between one electrode of the capacitor and the bit line is established, and the transfer of charges to and from the capacitor is allowed.
To increase data storage capacity of memory in a single chip, one method is to increase its density. High-density memory not only can provide a compact structural design on a wafer, but can also save production cost. In general, the density of an integrated circuit device can be increased by reducing the wiring lines, the dimensions of a transistor gate or area occupation of a device isolation region. However, the reduction in dimensions for some circuit elements is always limited by some newly established set of design rules because of miniaturization.
Following the set of design rules for producing a conventional miniaturized planar capacitor, the quantity of charges capable of being stored in a capacitor is greatly reduced. When the charge storage capacity of a capacitor is reduced, a number of problems will arise. For example, since a greater proportion of charges will be lost per unit time, potential drops quickly leading to a deterioration of memory function. Consequently, refresh cycles for DRAMs have to be performed more frequently. Since no data storage or retrieval can be done during these refresh cycles, frequent refreshes represents additional operational overhead. In addition, a reduction of charge storage capacity in a capacitor will result in a drop in potential. A low potential requires a rather complicated data processing design and a highly sensitive charge sense amplifier for reading out the charge from the capacitor. Therefore, complicated capacitor structures having large three dimensional charge storage surface must be designed in order to increase the capacitance as well as to fit them within the limited DRAM substrate surface caused by device miniaturization. However, forming these highly complicated capacitor structures is difficult, especially when quality and throughput are also required.
Forming hemispherical grained polysilicon (HSG-Si) layer over the charge-storage electrode surface of a DRAM capacitor is a widely adopted method for increasing capacitance nowadays. Conventionally, DRAM capacitors are formed by forming two polysilicon electrodes with a dielectric layer sandwiched in the middle. When the polysilicon electrodes are planarized in a conventional method, their surfaces are usually smooth. Hemispherical grained polysilicon is a special form of polysilicon having a rough surface. When the HSG-Si is deposited over the electrode under careful control, charge storage capacity of a DRAM capacitor can increase up to about 1.8 times.
To increase surface area of a capacitor even further, pillar-shaped or fin-shaped structures can be formed over the semiconductor base first before the deposition of HSG. However, fabricating pillar-shaped or fin-shaped involved complicated processing steps, which not only will lower the rate of production, but will also incur more cost as well.
In light of the foregoing, there is a need to improve the method of forming the lower electrode of a semiconductor capacitor.